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delayed control-transfer

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<architecture> A technique used on the SPARC processor to reduce the effect of pipeline breaks by executing the instruction after a branch instruction (the "delay instruction" in the "delay slot"). If there is no useful instruction which can be placed in the delay slot then the "annul bit" on the control transfer instruction can be set, preventing execution of the delay instruction (unless the control transfer is conditional and is taken).

Annulled branches are indicated in SPARC assembler language by appending ",A" to the operation code. For example,

 LOOP: ...
 CMP    %L0,10
 ADD     %L2, %L3, #L4

If the delay instruction is also a control transfer instruction then it gets more complicated. Both control transfer instructions are executed (but not the following instruction) and, assuming they are both taken, control is transferred briefly to the destination of the first and then immediately to the destination of the second.


Nearby terms: dehose « DEK « Delaunay triangulation « delayed control-transfer » delay instruction » delay slot » delete

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