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Each device has four JTAG control lines. There is a
common reset (TRST) and clock (TCLK). The data line
daisy chains one device's test data out (TDO) pin
to the test data in (TDI) pin on the next device.
The protocol contains commands to read and set the values of
the pins (and, optionally internal registers) of devices.
This is called "boundary scanning". The protocol makes
board testing easier as signals that are not visible at the
board connector may be read and set.
The protocol also allows the testing of equipment, connected
to the JTAG port, to identify components on the board (by
reading the device identification register) and to control and
monitor the device's outputs.
JTAG is not used during normal operation of a board.
JTAG Technologies B.V. (http://jtag.com/).
Boundary Scan/JTAG Technical Information - Xilinx, Inc. (http://xilinx.com/support/techsup/journals/jtag/).
Java API for Boundary Scan FAQs - Xilinx Inc. (http://xilinx.com/products/software/sx/sxfaqs.htm).
JTAG Boundary-Scan Test Products - Corelis, Inc. (http://corelis.com/products/scanovrv.html).
{"Logic analyzers stamping out bugs at the cutting edge", EDN Access, 1997-04-10
(http://ednmag.com/ednmag/reg/1997/041097/08df_02.htm)}.
{IEEE 1149.1 Device Architecture - Boundary-Scan Tutorial from ASSET InterTech, Inc.
(http://asset-intertech.com/tutorial/arch.htm)}.
{"Application-Specific Integrated Circuits", Michael John Sebatian Smith, published Addison-Wesley - Design Automation
Cafe
(http://dacafe.com/DACafe/EDATools/EDAbooks/ASIC/Book/CH14/CH14.2.htm)}.
Software Debug options on ASIC cores - Embedded Systems Programming Archive (http://embedded.com/97/feat9701.htm).
{Designing for On-Board Programming Using the IEEE 1149.1 (JTAG) Access Port - Intel
(http://developer.intel.com/design/flcomp/applnots/292186.htm)}.
{Built-In Self-Test Using Boundary Scan by Texas Instruments - EDTN Network
(http://edtn.com/scribe/reference/appnotes/md003e9a.htm)}.
(1999-11-15)
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